`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/06 15:38:40
// Design Name: 
// Module Name: reg8file_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module reg8file_sim();
    // Inputs
    reg clk = 1'b0;
    reg clrn = 1'b1;
    reg wen = 1'b1;
    reg [7:0] d = 8'b1;
    reg [2:0] wsel = 3'b000;
    reg [2:0] rsel = 3'b000;
    // Output
    wire [7:0] q;

	reg8file UUT(.clk(clk), .clrn(clrn), .wen(wen), .d(d) , .wsel(wsel), .rsel(rsel), .q(q));
	
	always #5 begin clk = ~clk; end
	
	initial begin
	    // initial: READ reg0
	    #2 begin clrn = 1'b1; wen = 1'b0; end                                   // FOLLOW/WRITE reg0 = 8'b0000_0001
	    #10 begin d = 8'b1111_0000; wsel = 3'b110; end                          // FOLLOW/WRITE reg6 = 0'b1111_0000
        #10 begin rsel = 3'b110; end                                            // READ reg6
        #2 begin clrn = 1'b0; end                                               // ASYNC SETZ
        #13 begin rsel = 3'b000; end                                            // READ reg0: check if reg0 is cleared
        #7 begin wen = 1'b0; wsel = 3'b011; d=8'b1111_0011; clrn = 1'b1; end   // FOLLOW/WRITE reg3 = 0'b1111_0011
        #10 begin wen = 1'b1; rsel = 3'b011; end                                // READ reg3
        #10 begin d = 8'b0101_0101; end                                         // KEEP reg3
        #10 $stop;
    end
    
endmodule
